Multi-core LSI Lifetime Extension by NBTI-Recovery-based Self-healing

1. Introduction Designing reliable systems has become more difficult in recent years. Besides conventional problems such as transistor leakage, the degradation and variation of transistor performance have a severe impact on the dependability of VLSI systems[1]-[3]. Negative-Bias-Temperature-Instability (NBTI) is one of the strongest reliability concerns for CMOS circuits[4][5]. Remarkable phenomena on NBTI is that degraded performance of a PMOS transistor recovers when the bias-temperature stress to the gate oxide is removed or relaxed. In this paper, we describe multi-core LSI lifetime extension method. In the following, it is shown that LSI lifetime is extended by combining NBTI recovery and circuit parallelization. It is a crucial step for this lifetime extension method to clarify the amount of NBTI recovery. So we characterize NBTI by a very short measurement delay (400 ns) NBTI sensor[6]. It is generally believed that the measurement delay is set to as short as 1 μs to avoid NBTI recovery for the correct NBTI characterization. It is also shown for the first time that transforming silicon area into LSI reliability is a promising and realistic concept for the ever-shrinking CMOS technology. 2. Lifetime Extension by NBTI Recovery Fig. 1 shows that an LSI performance degrades with time and finally reaches to its lifetime, for example, 10 years that is defined by the lower limit of LSI performance. If LSI performance is recovered with NBTI recovery, its lifetime can be further extended as shown in Fig. 1. As a result, it is a crucial step for this lifetime extension method with NBTI recovery to clarify the amount of NBTI recoverable component. The nature of the recoverable component is clarified with measurement results in section 4.